mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 PS21204 integrated power functions 600v/15a low-loss 3rd generation igbt inverter bridge for 3 phase dc-to-ac power conversion (fig. 2) application motor ratings : power : 0.75kw, sinusoidal, pwm frequency=5khz 100% load current : 5.0a (rms)* 150% load current : 7.5a (rms)*, 1 minute. *(note) : the motor current is assumed to be sinusoidal and the peak current value is defined as : l o 5 2 application ac100v~200v three-phase inverter drive for small power (0.75 kw) motor control. fig. 1 package outlines mitsubishi semiconductor PS21204 transfer-mold type insulated type integrated drive, protection and system control functions ? for upper-leg igbt s : drive circuit, high voltage isolated high-speed level shifting, control circuit under-voltage (uv) protection. note : bootstrap supply scheme can be applied (fig. 2). ? for lower-leg igbt s : drive circuit, control curcuit under-voltage protection (uv), short circuit protection (sc). (fig. 3) ? fault signaling : corresponding to a sc fault (low-side igbt) or a uv fault (low-side supply). ? input interface : 5v line cmos/ttl compatible, schmitt trigger receiver circuit. ? 26 21 20 19 24 18 17 25 16 23 15 22 14 13 11 12 10 9 8 7 6 5 4 3 2 2.8 1 13.4 21.4 12.8 3.8 8 20 11.5 31 79 2- f 4.5 67 10 10 10 1. u p terminals code 4. v ufs 7. v vfb 10. v p1 13. v wfs 16. cin 19. u n 22. p 25. w 2. v p1 5. v p 8. v vfs 11. v pc 14. v n1 17. cfo 20. v n 23. u 26. n 3. v ufb 6. v p1 9. w p 12. v wfb 15. v nc 18. fo 21. w n 24. v
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 fig. 2 internal functions block diagram (typical application example) fig. 3 external part of the dip-ipm protection circuit z drive circuit cbu cbu+ cbv cbv+ cbw cbw+ (15v line) (5v line) (note 1, 2) v d v nc v nc w ac line input ac line output v u input signal coditioning level shifter drive circuit protection circuit (uv) input signal coditioning input signal coditioning input signal conditioning fo logic protection circuit protection circuit (uv) protection circuit (uv) control supply under-voltage protection drive circuit drive circuit f o cfo p n 1 n fault output (5v line) (note 3, 5) high-side input (pwm) (5v line) note 1,2) low-side input (pwm) m (note 6) bootstrap circuit for detailed description of the boot-strap circuit construction, please contact mitsubishi electric dip-ipm c z : znr (surge absorber) c : ac filter (ceramic capacitor 2.2~6.5nf) (note : additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). c4 c3 c3 : tight tolerance, temp-compensated electrolytic type c4 : 0.22~2 m f r-category ceramic capacitor for noise filtering. (note : the capacitance value depends on the pwm control scheme used in the applied system). note1: to prevent the input signals oscillation, an rc coupling at each input is recommended. (see also fig. 7) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto-coupler or transformer isolation is possible. (see also fig. 7) 3: this output is open collector type. the signal line should be pulled up to the positive side of the 5v power supply with a pproximately 5.1k w resistance. (see also fig. 7) 4: the wiring between the power dc link capacitor and the p/n1 terminals should be as short as possible to protect the dip-ipm against catastrophic high surge voltages. for extra precaution, a small film type snubber capacitor (0.1~0.22 m f, high voltage type) is recommended to be mounted close to these p and n1 dc power input pins. 5: fo output pulse width should be decided by putting external capacitor between cfo and v nc terminals. (example : cfo=22nf t fo =1.8ms (typ.)) 6: high voltage diodes (600v or more) should be used in the bootstrap circuit. h-side igbt s l-side igbt s cin (note 4) fig. 3 inrush current limiter circuit level shifter level shifter note1: in the recommended external protection circuit, please select the rc time constant in the range 1.5~2.0 m s. 2: to prevent erroneous protection operation, the wiring of a, b, c should be as short as possible. drive circuit drive circuit protection circuit w v u b c v nc cin a p n1 n c r shunt resistor external protection circuit dip-ipm l-side igbt s h-side igbt s sc protection trip level i c (a) t w ( m s) 2 0 short circuit protective function (sc) : sc protection is achieved by sensing the l-side dc-bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the rc circuit). when the sensed shunt voltage exceeds the sc trip-level, all the l-side igbts are turned off and a fault signal (fo) is output. since the sc fault may be repetitive, it is recommended to stop the system when the fo signal is received and check the fault. collector current waveform
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 400 C20~+100 C40~+125 1500 v d = v db = 13.5~16.5v, inverter part t j = 125c, non-repetitive, less than 2 m s (note 2) 60hz, sinusoidal, ac 1 minute, connection pins to heat-sink plate v cc(prot) t c t stg v iso v v v v ma v 20 20 C0.5~+5.5 C0.5~v d +0.5 15 C0.5~v d +0.5 applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between u p , v p , w p -v pc , u n , v n , w n -v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v cin v fo i fo v sc 450 500 600 15 30 43 C20~+150 applied between p-n applied between p-n t c = 25c t c = 25c, instantaneous value (pulse) t c = 25c, per 1 chip (note 1) v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w c maximum ratings (t j = 25c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part symbol ratings unit self protection supply voltage limit (short circuit protection capability) module case operation temperature storage temperature isolation voltage v c c v rms total system note 1 : the maximum junction temperature rating of the power chips integrated within the dip-ipm is 150c (@ t c 100c) however, to in- sure safe operation of the dip-ipm, the average junction temperature should be limited to t j(ave) 125c (@ t c 100c). parameter condition note 2 : t c measurement point control pins power pins tc heat sink boundary dip-ipm
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 13.5 13.5 4.9 0.8 3.0 0.45 10.0 10.5 10.3 10.8 1.0 0.8 2.5 0.8 2.5 ma v t j = 25c t j = 125c i c = 15a, t j = 25c i c = 15a, t j = 125c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces condition symbol parameter limits inverter igbt part (per 1/6 module) inverter fwdi part (per 1/6 module) case to fin, (per 1 module) thermal grease applied r th(j-c)q r th(j-c)f r th(c-f) min. c/w thermal resistance typ. max. 2.85 4.5 0.067 unit t j = 25c, Ci c = 15a, v cin = 5v condition symbol parameter limits min. typ. max. unit electrical characteristics (t j = 25c, unless otherwise noted) inverter part collector-emitter saturation voltage fwdi forward voltage junction to case thermal resistance contact thermal resistance v d = v db = 15v v cin = 0v switching times v cc = 300v, v d = v db = 15v i c = 15a, t j = 125c, v cin = 5v ? 0v inductive load (upper-lower arm) note : t on , t off include delay time of the internal control circuit collector-emitter cut-off current v ce = v ces 1.8 2.0 2.2 0.7 0.1 0.4 1.9 0.9 1.0 10 v m s note 2 : short circuit protection is functioning only at the low-arms. please select the value of the external shunt resistor such that the sc trip- level is less than 25.5 a. 3: fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. the fault output pulse- width t fo depends on the capacitance value of c fo according to the following approximate equation : c fo = 12.2 5 10 -6 5 t fo [f]. applied between: u p , v p , w p -v pc applied between: u n , v n , w n -v nc trip level reset level trip level reset level v p1 -v pc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs v p1 -v pc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs control supply voltage control supply voltage circuit current condition symbol parameter limits v d v db i d v foh v fol v fosat f pwm t dead v sc(ref) uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) v th(on) v th(off) min. typ. max. unit control (protection) part v d = v db = 15v, input = off v d = v db = 15v, input = on v sc = 0v, f o circuit : 10k w to 5v pull-up v sc = 1v, f o circuit : 10k w to 5v pull-up v sc = 1v, i fo = 15ma t c 100c, t j 125c relates to corresponding input signal for blocking arm shoot-through. C20c t c 100c t j = 25c, v d = 15c (note 2) fault output voltage pwm input frequency allowable deadtime short circuit trip level supply circuit under-voltage protection t j 125c fault output pulse width (note 3) on threshold voltage off threshold voltage on threshold voltage off threshold voltage c fo = 22nf (connected between cfoCv nc ) h-side l-side 15.0 15.0 4.25 0.50 4.95 0.50 1.0 1.2 5.0 0.5 1.8 1.4 3.0 1.4 3.0 16.5 16.5 8.50 1.00 9.70 1.00 2.0 1.8 0.55 12.0 12.5 12.5 13.0 2.0 4.0 2.0 4.0 v v ma ma ma ma v v v khz m s v v v v v ms v v
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 400 16.5 16.5 1.0 mounting screw : m4 condition parameter limits mounting torque weight min. mechanical characteristics and ratings typ. max. 10 0.98 unit recommended 12kgcm recommended 1.18nm 54 15 1.47 kgcm nm g v cc v d v db d v d , d v db t dead f pwm v cin(on) v cin(off) applied between p-n applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs for each input signal t c 100c, t j 125c applied between u p , v p , w p -v pc applied between u n , v n , w n -v nc condition symbol parameter limits min. typ. max. 0 13.5 13.5 C1 3 unit recommended operation conditions supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency input on threshold voltage input off threshold voltage 300 15.0 15.0 5 v v v v/ m s m s khz v v 0~0.65 4.0~5.5 ho dip-ipm in com u out v out w out v no cfo gnd fo w n v n u n v cc hvic 3 hvic 2 hvic 1 lvic cfo cin cin n w v u p v s v b v cc ho in com v s v b v cc ho in com v s v b v cc fo w n v n u n w p v p u p v nc v n1 v pc v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb fig. 4 the dip-ipm internal circuit
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 fig. 5 timing charts of the dip-ipm protective functions [a] short-circuit protection (lower-arms only) (for the external shunt resistance and cr connection, please refer to fig. 3.) a1. normal operation : igbt on and carrying current. a2. short circuit current detection (sc trigger). a3. hard igbt gate interrupt. a4. igbt turns off. a5. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a6. input h : igbt off state. a7. input l : igbt on state, but during the f o active signal the igbt doesnt turn on. a8. igbt off state. [b] under-voltage protection (n-side, uv d ) a1. normal operation : igbt on and carrying current. a2. under voltage trip (uv dt ). a3. igbt off inspite of control input condition. a4. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a5. under voltage reset (uv dr ). a6. normal operation : igbt on and carrying current. note : the cr time constant safe guards against erroneous sc fault signals resulting from di/dt generated voltages when the igbt turn s on. the optimum setting for the cr circuit time constant is 1.5~2.0 m s. error output fo sense voltage of the shunt resistance sc reference voltage cr circuit time constant delay ( * note) output current ic(a) internal igbt gate protection circuit state lower-arms control input a5 a8 a4 a3 a1 a2 sc reset set a7 a6 error output fo (n-side only) output current ic(a) control supply voltage v d protection circuit state control input a6 a1 a3 a5 a2 reset uv dt uv dr set a4
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 [c] under-voltage protection (p-side, uv db ) a1. control supply voltage rises : after the voltage level reachs uv dbr , the circuits start to operate when the next input is applied. a2. normal operation : igbt on and carrying current. a3. under voltage trip (uv dbt ). a4. igbt off inspite of control input condition, but there is no f o signal output. a5. under-voltage reset (uv dbr ). a6. normal operation : igbt on and carrying current. fig. 7 recommended cpu i/o interface circuit note : rc coupling at each input (parts shown dotted) may change depending on the pwm control scheme used in the application and on the wiring impedances of the applications printed circuit board. error output fo output current ic(a) control supply voltage v db protection circuit state control input a6 a1 a2 a4 a5 a3 reset uv dbt uv dbr set reset high-level (no fault output) cpu 4.7k w 5.1k w 5v line 1nf 1nf u p ,v p ,w p ,u n ,v n ,w n v nc (logic) fo dip-ipm
mitsubishi semiconductor PS21204 transfer-mold type insulated type aug. 1999 fig. 8 typical dip-ipm application circuit example note 1 : to prevent the input signals oscillation, an rc coupling at each input is recommended, and the wiring of each input should be a s short as possible. (less than 2cm) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto -coupler or transformer isolation is possible. 3: f o output is open collector type. this signal line should be pulled up to the positive side of the 5v power supply with approxima tely 5.1k w resistance. 4: f o output pulse width should be decided by connecting an external capacitor between cfo and v nc terminals (c fo ). (example : c fo = 22 nf ? t fo = 1.8 ms (typ.)) 5: each input signal line should be pulled up to the 5v power supply with approximately 4.7k w resistance (other rc coupling circuits at each input may be needed depending on the pwm control scheme used and on the wiring impedances of the systems printed circuit board). approximately a 0.22~2 m f by-pass capacitor should be used across each power supply connection terminals. 6: to prevent errors of the protection function, the wiring of a, b, c should be as short as possible. 7: in the recommended protection circuit, please select the r 1 c 5 time constant in the range 1.5~2 m s. 8: each capacitor should be put as nearby the pins of the dip-ipm as possible. 9: to prevent surge destruction, the wiring between the smoothing capacitor and the p&n1 pins should be as short as possible. appr oxi- mately a 0.1~0.22 m f snubber capacitor between the p&n1 pins is recommended. ho ho dip-ipm c1: tight to lerance temp - compensated electrolytic type; c2,c3: 0. 22~2 m f r - category ceramic capacitor for noise filtering (note : the capacitance value depends on the pwm control used in the applied system) c3 c3 c3 c3 c2 c2 c2 c1 c1 c1 ho in in 15v line 5v line 5v line in com com com u out v out w out v no cfo gnd f o w n v n v cc c b a c4(c fo ) cfo r1 c5 shunt resistor cin cin n1 n w v u p v s v s v s v b v b v b v cc v cc v cc fo w n v n u n u n w p v p u p v nc v n1 v pc v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb m r sh for detailed description of the boot - strap circuit construction, please contact mitsubishi electric c p u u n i t
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